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1 features ? compatible with mcs-51 ? products 8k bytes of in-system programmable (isp) flash memory ? endurance: 1000 write/erase cycles 4.0v to 5.5v operating range fully static operation: 0 hz to 33 mhz three-level program memory lock 256 x 8-bit internal ram 32 programmable i/o lines three 16-bit timer/counters eight interrupt sources full duplex uart serial channel low-power idle and power-down modes interrupt recovery from power-down mode watchdog timer dual data pointer power-off flag description the at89s52 is a low-power, high-performance cmos 8-bit microcontroller with 8k bytes of in-system programmable flash memory. the device is manufactured using atmel?s high-density nonvolatile memory technology and is compatible with the indus- try-standard 80c51 instruction set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro- grammer. by combining a versatile 8-bit cpu with in-system programmable flash on a monolithic chip, the atmel at89s52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. the at89s52 provides the following standard features: 8k bytes of flash, 256 bytes of ram, 32 i/o lines, watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. in addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port, and interrupt system to continue functioning. the power-down mode saves the ram con- tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. rev. 1919a-07/01 8-bit microcontroller with 8k bytes in-system programmable flash at89s52
at89s52 2 tqfp 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd gnd (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 plcc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 p1.4 p1.3 p1.2 p1.1 (t2 ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) pin configurations pdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2 ex) p1.1 p1.2 p1.3 p1.4 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8)
at89s52 3 block diagram port 2 drivers port 2 latch p2.0 - p2.7 flash port 0 latch ram program address register buffer pc incrementer program counter dual dptr instruction register b register interrupt, serial port, and timer blocks stack pointer acc tmp2 tmp1 alu psw timing and control port 1 drivers p1.0 - p1.7 port 3 latch port 3 drivers p3.0 - p3.7 osc gnd v cc psen ale/prog ea / v pp rst ram addr. register port 0 drivers p0.0 - p0.7 port 1 latch watch dog isp port program logic
at89s52 4 pin description vcc supply voltage. gnd ground. port 0 port 0 is an 8-bit open drain bidirectional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high- impedance inputs. port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external program and data memory. in this mode, p0 has internal pullups. port 0 also receives the code bytes during flash program- ming and outputs the code bytes during program verifica- tion. external pullups are required during program verification. port 1 port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are exter nally being pulled low will source current (i il ) because of the internal pullups. in addition, p1.0 and p1.1 can be configured to be the timer/counter 2 external count input (p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex), respectively, as shown in the following table. port 1 also receives the low-order address bytes during flash programming and verification. port 2 port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are exter nally being pulled low will source current (i il ) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application, port 2 uses strong internal pul- lups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification. port 3 port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are extern ally being pulled low will source current (i il ) because of the pullups. port 3 also serves the functions of various special features of the at89s52, as shown in the following table. port 3 also receives some control signals for flash pro- gramming and verification. rst reset input. a high on this pin for two machine cycles while the oscillator is running resets the device. this pin drives high for 96 oscillator periods after the watchdog times out. the disrto bit in sfr auxr (address 8eh) can be used to disable this feature. in the default state of bit disrto, the reset high out feature is enabled. ale/prog address latch enable (ale) is an output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog ) during flash programming. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only dur- ing a movx or movc instruction. otherwise, the pin is port pin alternate functions p1.0 t2 (external count input to timer/counter 2), clock-out p1.1 t2ex (timer/counter 2 capture/reload trigger and direction control) p1.5 mosi (used for in-system programming) p1.6 miso (used for in-system programming) p1.7 sck (used for in-system programming) port pin alternate functions p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe)
at89s52 5 weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode. psen program store enable (psen) is the read strobe to exter- nal program memory. when the at89s52 is executi ng code from external pro- gram memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. ea /vpp external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external pro- gram memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to v cc for internal program execu- tions. this pin also receives the 12-volt programming enable volt- age (v pp ) during flash programming. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. table 1. at89s52 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 0d7h 0c8h t2con 00000000 t2mod xxxxxx00 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 0cfh 0c0h 0c7h 0b8h ip xx000000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0x000000 0afh 0a0h p2 11111111 auxr1 xxxxxxx0 wdtrst xxxxxxxx 0a7h 98h scon 00000000 sbuf xxxxxxxx 9fh 90h p1 11111111 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 auxr xxx00xx0 8fh 80h p0 11111111 sp 00000111 dp0l 00000000 dp0h 00000000 dp1l 00000000 dp1h 00000000 pcon 0xxx0000 87h
at89s52 6 special function registers a map of the on-chip memory area called the special func- tion register (sfr) space is shown in table 1. note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. user software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0. timer 2 registers: control and status bits are contained in registers t2con (shown in table 2) and t2mod (shown in table 3) for timer 2. the register pair (rcap2h, rcap2l) are the capture/reload registers for timer 2 in 16-bit cap- ture mode or 16-bit auto-reload mode. interrupt registers: the individual interrupt enable bits are in the ie register. two priorities can be set for each of the six interrupt sources in the ip register. table 2. t2con ? timer/counter 2 control register t2con address = 0c8h reset value = 0000 0000b bit addressable bit tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 76543210 symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk receive clock enable. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk transmit clock enable. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in serial por t modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 timer 2 external enable. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if tim er 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. tr2 = 1 starts the timer. c/t2 timer or counter select for timer 2. c/t2 = 0 for timer function. c/t2 = 1 for external event counter (falling edge triggered). cp/rl2 capture/reload select. cp/rl2 = 1 causes captures to occur on negative transitions at t2ex if exen2 = 1. cp/rl2 = 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at t2ex when exen2 = 1. when either rclk or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow.
at89s52 7 dual data pointer registers: to facilitate accessing both internal and external data memory, two banks of 16-bit data pointer registers are provided: dp0 at sfr address locations 82h-83h and dp1 at 84h-85h. bit dps = 0 in sfr auxr1 selects dp0 and dps = 1 selects dp1. the user should always initialize the dps bit to the appropriate value before accessing the respective data pointer register. power off flag: the power off flag (pof) is located at bit 4 (pcon.4) in the pcon sfr. pof is set to ?1? during power up. it can be set and rest under software control and is not affected by reset. table 3a. auxr: auxiliary register auxr address = 8eh reset value = xxx00xx0b not bit addressable ? ? ? wdidle disrto ? ? disale bit 7 6 5 4 3 2 1 0 ? reserved for future expansion disale disable/enable ale disale operating mode 0 ale is emitted at a constant rate of 1/6 the oscillator frequency 1 ale is active only during a movx or movc instruction disrto disable/enable reset out disrto 0 reset pin is driven high after wdt times out 1 reset pin is input only wdidle disable/enable wdt in idle mode wdidle 0 wdt continues to count in idle mode 1 wdt halts counting in idle mode table 3b. auxr1: auxiliary register 1 auxr1 address = a2h reset value = xxxxxxx0b not bit addressable ??? ? ? ? ?dps bit 7 6 5 4 3 2 1 0 ? reserved for future expansion dps data pointer register select dps 0 selects dptr registers dp0l, dp0h 1 selects dptr registers dp1l, dp1h
at89s52 8 memory organization mcs-51 devices have a separate address space for pro- gram and data memory. up to 64k bytes each of external program and data memory can be addressed. program memory if the ea pin is connected to gnd, all program fetches are directed to external memory. on the at89s52, if ea is connected to v cc , program fetches to addresses 0000h through 1fffh are directed to internal memory and fetches to addresses 2000h through ffffh are to external memory. data memory the at89s52 implements 256 bytes of on-chip ram. the upper 128 bytes occupy a parallel address space to the special function registers. this means that the upper 128 bytes have the same addresses as the sfr space but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the address mode used in the instruction specifies whether the cpu accesses the upper 128 bytes of ram or the sfr space. instructions which use direct addressing access of the sfr space. for example, the following direct addressing instruction accesses the sfr at location 0a0h (which is p2). mov 0a0h, #data instructions that use indirect addressing access the upper 128 bytes of ram. for example, the following indirect addressing instruction, where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). mov @r0, #data note that stack operations are examples of indirect addressing, so the upper 128 bytes of data ram are avail- able as stack space.
at89s52 9 watchdog timer (one-time enabled with reset-out) the wdt is intended as a recovery method in situations where the cpu may be subjected to software upsets. the wdt consists of a 13-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is defaulted to disable from exiting reset. to enable the wdt, a user must write 01eh and 0e1h in sequence to the wdtrst register (sfr location 0a6h). when the wdt is enabled, it will increment every machine cycle while the oscillator is run- ning. the wdt timeout period is dependent on the external clock frequency. there is no way to disable the wdt except through reset (either hardware reset or wdt over- flow reset). when wdt overflows, it will drive an output reset high pulse at the rst pin. using the wdt to enable the wdt, a user must write 01eh and 0e1h in sequence to the wdtrst register (sfr location 0a6h). when the wdt is enabled, the user needs to service it by writing 01eh and 0e1h to wdtrst to avoid a wdt over- flow. the 13-bit counter overflows when it reaches 8191 (1fffh), and this will reset the device. when the wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 8191 machine cycles. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write-only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96xtosc, where tosc=1/fosc. to make the best use of the wdt, it should be serviced in those sec- tions of code that will periodically be executed within the time required to prevent a wdt reset. wdt during power-down and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode, the user does not need to service the wdt. there are two methods of exiting power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as it normally does whenever the at89s52 is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabi- lize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service for the interrupt used to exit power-down mode. to ensure that the wdt does not overflow within a few states of exiting power-down, it is best to reset the wdt just before entering power-down mode. before going into the idle mode, the wdidle bit in sfr auxr is used to determine whether the wdt continues to count if enabled. the wdt keeps counting during idle (wdidle bit = 0) as the default state. to prevent the wdt from resetting the at89s52 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and reenter idle mode. with wdidle bit enabled, the wdt will stop to count in idle mode and resumes the count upon exit from idle. uart the uart in the at89s52 operates the same way as the uart in the at89c51 and at89c52. for further informa- tion on the uart operation, refer to the atmel web site (http://www.atmel.com). from the home page, select ?prod- ucts?, then ?8051-architecture flash microcontroller?, then ?product overview?. timer 0 and 1 timer 0 and timer 1 in the at89s52 operate the same way as timer 0 and timer 1 in the at89c51 and at89c52. for further information on the timers? operation, refer to the atmel web site (http://www.atmel.com). from the home page, select ?products?, then ?8051-architecture flash microcontroller?, then ?product overview?. timer 2 timer 2 is a 16-bit timer/counter that can operate as either a timer or an event counter. the type of operation is selected by bit c/t2 in the sfr t2con (shown in table 2). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. the modes are selected by bits in t2con, as shown in table 3. timer 2 consists of two 8-bit registers, th2 and tl2. in the timer function, the tl2 register is incremented every machine cycle. since a machine cycle consists of 12 oscil- lator periods, the count rate is 1/12 of the oscillator frequency. table 3. timer 2 operating modes rclk +tclk cp/rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off)
at89s52 10 in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transi- tion, the maximum count rate is 1/24 of the oscillator fre- quency. to ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. capture mode in the capture mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit tf2 in t2con. this bit can then be used to generate an interrupt. if exen2 = 1, timer 2 performs the same operation, but a 1- to-0 transition at external input t2ex also causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. the exf2 bit, like tf2, can generate an interrupt. the capture mode is illustrated in figure 5. auto-reload (up or down counter) timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. this feature is invoked by the dcen (down counter enable) bit located in the sfr t2mod (see table 4). upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down, depending on the value of the t2ex pin. figure 5. timer in capture mode figure 6 shows timer 2 automatically counting up when dcen=0. in this mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 counts up to 0ffffh and then sets the tf2 bit upon overflow. the overflow also causes the timer registers to be reloaded with the 16-bit value in rcap2h and rcap2l. the values in timer in capture modercap2h and rcap2l are preset by software. if exen2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input t2ex. this transition also sets the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer 2 to count up or down, as shown in figure 6. in this mode, the t2ex pin controls the direction of the count. a logic 1 at t2ex makes timer 2 count up. the timer will overflow at 0ffffh and set the tf2 bit. this overflow also causes the 16-bit value in rcap2h and rcap2l to be reloaded into the timer regis- ters, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. the timer underflows when th2 and tl2 equal the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes 0ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows and can be used as a 17th bit of resolution. in this operating mode, exf2 does not flag an interrupt. osc exf2 t2ex pin t2 pin tr2 exen2 c/t2 = 0 c/t2 = 1 control capture overflow control transition detector timer 2 interrupt 12 rcap2l rcap2h th2 tl2 tf2
at89s52 11 figure 6. timer 2 auto reload mode (dcen = 0) table 4. t2mod ? timer 2 mode control register osc exf2 tf2 t2ex pin t2 pin tr2 exen2 c/t2 = 0 c/t2 = 1 contr ol relo ad control transition detector timer 2 interrupt 12 rcap2l rcap2h th2 tl2 overflow t2mod address = 0c9h reset value = xxxx xx00b not bit addressable ??????t2oedcen bit76543210 symbol function ? not implemented, reserved for future t2oe timer 2 output enable bit dcen when set, this bit allows timer 2 to be configured as an up/down counter
at89s52 12 figure 7. timer 2 auto reload mode (dcen = 1) figure 8. timer 2 in baud rate generator mode osc exf2 tf2 t2ex pin count direction 1=up 0=down t2 pin tr2 control overflow toggle timer 2 interrupt 12 rcap2l rcap2h 0ffh 0ffh th2 tl2 c/t2 = 0 c/t2 = 1 (down counting reload value) (up counting reload value) osc smod1 rclk tclk rx clock tx clock t2ex pin t2 pin tr2 control "1" "1" "1" "0" "0" "0" timer 1 overflow note: osc. freq. is divided by 2, not 12 timer 2 interrupt 2 2 16 16 rcap2l rcap2h th2 tl2 c/t2 = 0 c/t2 = 1 exf2 control transition detector exen2
at89s52 13 baud rate generator timer 2 is selected as the baud rate generator by setting tclk and/or rclk in t2con (table 2). note that the baud rates for transmit and receive can be different if timer 2 is used for the receiver or transmitter and timer 1 is used for the other function. setting rclk and/or tclk puts timer 2 into its baud rate generator mode, as shown in fig- ure 8. the baud rate generator mode is similar to the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2?s overflow rate according to the following equation. the timer can be configured for either timer or counter operation. in most applications, it is configured for timer operation (cp/t2 = 0). the timer operation is different for timer 2 when it is used as a baud rate generator. normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). as a baud rate generator, however, it increments every state time (at 1/2 the oscillator fre- quency). the baud rate formula is given below. where (rcap2h, rcap2l) is the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. timer 2 as a baud rate generator is shown in figure 8. this figure is valid only if rclk or tclk = 1 in t2con. note that a rollover in th2 does not set tf2 and will not gener- ate an interrupt. note too, that if exen2 is set, a 1-to-0 transition in t2ex will set exf2 but will not cause a reload from (rcap2h, rcap2l) to (th2, tl2). thus, when timer 2 is in use as a baud rate generator, t2ex can be used as an extra external interrupt. note that when timer 2 is running (tr2 = 1) as a timer in the baud rate generator mode, th2 or tl2 should not be read from or written to. under these conditions, the timer is incremented every state time, and the results of a read or write may not be accurate. the rcap2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. figure 9. timer 2 in clock-out mode modes 1 and 3 baud rates timer 2 overflow rate 16 ----------------------------------------------------------- - = modes 1 and 3 baud rate --------------------------------------- oscillator frequency 32 x [65536-rcap2h,rcap2l)] ------------------------------------------------------------------------------------- - = osc exf2 p1.0 (t2) p1.1 (t2ex) tr2 exen2 c/t2 bit transition detector timer 2 interrupt t2oe (t2mod.1) 2 tl2 (8-bits) rcap2l rcap2h th2 (8-bits) 2
at89s52 14 programmable clock out a 50% duty cycle clock can be programmed to come out on p1.0, as shown in figure 9. this pin, besides being a regu- lar i/o pin, has two alternate functions. it can be pro- grammed to input the external clock for timer/counter 2 or to output a 50% duty cycle clock ranging from 61 hz to 4 mhz at a 16 mhz operating frequency. to configure the timer/counter 2 as a clock generator, bit c/t2 (t2con.1) must be cleared and bit t2oe (t2mod.1) must be set. bit tr2 (t2con.2) starts and stops the timer. the clock-out frequency depends on the oscillator fre- quency and the reload value of timer 2 capture registers (rcap2h, rcap2l), as shown in the following equation. in the clock-out mode, timer 2 roll-overs will not generate an interrupt. this behavior is similar to when timer 2 is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simulta- neously. note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use rcap2h and rcap2l. interrupts the at89s52 has a total of six interrupt vectors: two exter- nal interrupts (int0 and int1 ), three timer interrupts (tim- ers 0, 1, and 2), and the serial port interrupt. these interrupts are all shown in figure 10. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie. ie also contains a global disable bit, ea, which disables all interrupts at once. note that table 5 shows that bit position ie.6 is unimple- mented. in the at89s52, bit position ie.5 is also unimple- mented. user software should not write 1s to these bit positions, since they may be used in future at89 products. timer 2 interrupt is generated by the logical or of bits tf2 and exf2 in register t2con. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt, and that bit will have to be cleared in software. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in which the timers overflow. the values are then polled by the circuitry in the next cycle. however, the timer 2 flag, tf2, is set at s2p2 and is polled in the same cycle in which the timer overflows. table 5. interrupt enable (ie) register figure 10. interrupt sources clock-out frequency oscillator frequency 4 x [65536-(rcap2h,rcap2l)] ------------------------------------------------------------------------------------ - = (msb) (lsb) ea ? et2 es et1 ex1 et0 ex0 enable bit = 1 enables the interrupt. enable bit = 0 disables the interrupt. symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt is acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ? ie.6 reserved. et2 ie.5 timer 2 interrupt enable bit. es ie.4 serial port interrupt enable bit. et1 ie.3 timer 1 interrupt enable bit. ex1 ie.2 external interrupt 1 enable bit. et0 ie.1 timer 0 interrupt enable bit. ex0 ie.0 external interrupt 0 enable bit. user software should never write 1s to unimplemented bits, because they may be used in future at89 products. ie1 ie0 1 1 0 0 tf1 tf0 int1 int0 ti ri tf2 exf2
at89s52 15 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in figure 11. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven, as shown in figure 12. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi- mum voltage high and low time specifications must be observed. idle mode in idle mode, the cpu puts itself to sleep while all the on- chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the spe- cial functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle mode is termi- nated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to exter- nal memory. power-down mode in the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function regis- ters retain their values until the power-down mode is termi- nated. exit from power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. figure 11. oscillator connections note: c1, c2 = 30 pf 10 pf for crystals = 40 pf 10 pf for ceramic resonators figure 12. external clock drive configuration c2 xtal2 gnd xtal1 c1 xtal2 xtal1 gnd nc external oscillator signal table 6. status of external pins during idle and power-down modes mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
at89s52 16 program memory lock bits the at89s52 has three lock bits that can be left unpro- grammed (u) or can be programmed (p) to obtain the addi- tional features listed in the following table. when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. the latched value of ea must agree with the current logic level at that pin in order for the device to function properly. programming the flash ? parallel mode the at89s52 is shipped with the on-chip flash memory array ready to be programmed. the programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party flash or eprom programmers. the at89s52 code memory array is programmed byte-by- byte. programming algorithm: before programming the at89s52, the address, data, and control signals should be set up according to the flash programming mode table and figures 13 and 14. to program the at89s52, take the fol- lowing steps: 1. input the desired memory location on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control signals. 4. raise ea /v pp to 12v. 5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 50 s. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. data polling: the at89s52 features data polling to indi- cate the end of a byte write cycle. during a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on p0.7. once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated. ready/busy : the progress of byte programming can also be monitored by the rdy/bsy output signal. p3.0 is pulled low after ale goes high during programming to indicate busy . p3.0 is pulled high again when programming is done to indicate ready. program verify: if lock bits lb1 and lb2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the status of the individual lock bits can be verified directly by reading them back. reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 000h, 100h, and 200h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows. (000h) = 1eh indicates manufactured by atmel (100h) = 52h indicates 89s52 (200h) = 06h chip erase: in the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ale/prog low for a dura- tion of 200 ns - 500 ns. in the serial programming mode, a chip erase operation is initiated by issuing the chip erase instruction. in this mode, chip erase is self-timed and takes about 500 ms. during chip erase, a serial read from any address location will return 00h at the data output. programming the flash ? serial mode the code memory array can be programmed using the serial isp interface while rst is pulled to v cc . the serial interface consists of pins sck, mosi (input) and miso (output). after rst is set high, the programming enable instruction needs to be executed first before other opera- tions can be executed. before a reprogramming sequence can occur, a chip erase operation is required. the chip erase operation turns the content of every mem- ory location in the code array into ffh. either an external system clock can be supplied at pin xtal1 or a crystal needs to be connected across pins xtal1 and xtal2. the maximum serial clock (sck) table 7. lock bit protection modes program lock bits lb1 lb2 lb3 protection type 1 u u u no program lock features 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the flash memory is disabled 3 p p u same as mode 2, but verify is also disabled 4 p p p same as mode 3, but external execution is also disabled
at89s52 17 frequency should be less than 1/16 of the crystal fre- quency. with a 33 mhz oscillator clock, the maximum sck frequency is 2 mhz. serial programming algorithm to program and verify the at89s52 in the serial program- ming mode, the following sequence is recommended: 1. power-up sequence: apply power between vcc and gnd pins. set rst pin to ?h?. if a crystal is not connected across pins xtal1 and xtal2, apply a 3 mhz to 33 mhz clock to xtal1 pin and wait for at least 10 milliseconds. 2. enable serial programming by sending the pro- gramming enable serial instruction to pin mosi/p1.5. the frequency of the shift clock sup- plied at pin sck/p1.7 needs to be less than the cpu clock at xtal1 divided by 16. 3. the code array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. the write cycle is self- timed and typically takes less than 1 ms at 5v. 4. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso/p1.6. 5. at the end of a programming session, rst can be set low to commence normal device operation. power-off sequence (if needed): set xtal1 to ?l? (if a crystal is not used). set rst to ?l?. turn v cc power off. data polling: the data polling feature is also available in the serial mode. in this mode, during a write cycle an attempted read of the last byte written will result in the com- plement of the msb of the serial output byte on miso. serial programming instruction set the instruction set for serial programming follows a 4-byte protocol and is shown in table 10.
at89s52 18 programming interface ? parallel mode every code byte in the flash array can be programmed by using the appropriate combination of control signals. the write operation cycle is self-timed and once initiated, will automatically time itself to completion. all major programming vendors offer worldwide support for the atmel microcontroller series. please contact your local programming vendor for the appropriate software revision. notes: 1. each prog pulse is 200 ns - 500 ns for chip erase. 2. each prog pulse is 200 ns - 500 ns for write code data. 3. each prog pulse is 200 ns - 500 ns for write lock bits. 4. rdy/bsy signal is output on p3.0 during programming. 5. x = don?t care. figure 13. programming the flash memory (parallel mode) figure 14. verifying the flash memory (parallel mode) table 8. flash programming modes mode v cc rst psen ale/ prog ea / v pp p2.6 p2.7 p3.3 p3.6 p3.7 p0.7-0 data p2.4-0 p1.7-0 address write code data 5v h l (2) 12v lhhhh d in a12-8 a7-0 read code data 5v h l h h l l l h h d out a12-8 a7-0 write lock bit 1 5v h l (3) 12vhhhhh x x x write lock bit 2 5v h l (3) 12v h h h l l x x x write lock bit 3 5v h l (3) 12v h l h h l x x x read lock bits 1, 2, 3 5v h l h h h h l h l p0.2, p0.3, p0.4 xx chip erase 5v h l (1) 12vhlhll x x x read atmel id 5v h l h h lllll 1ehx 0000 00h read device id 5v h l h h lllll 52hx 0001 00h read device id 5v h l h h lllll 06hx 0010 00h p1.0-p1.7 p2.6 p3.6 p2.0 - p2.4 a0 - a7 addr. 0000h/1fffh see flash programming modes table 3-33 mhz p0 v p2.7 pgm data prog v/v ih pp v ih ale p3.7 xtal2 ea rst psen xtal 1 gnd v cc at89s52 p3.3 p3.0 rdy/ bsy a8 - a12 cc p1.0-p1.7 p2.6 p3.6 p2.0 - p2.4 a0 - a7 addr. 0000h/1fffh see flash programming modes table 3-33 mhz p0 p2.7 pgm data (use 10k pullups) v ih v ih ale p3.7 xtal 2 ea rst psen xtal1 gnd v cc at89s52 p3.3 a8 - a12 v cc
at89s52 19 figure 15. flash programming and verification waveforms ? parallel mode flash programming and verification characteristics (parallel mode) t a = 20c to 30c, v cc = 4.5 to 5.5v symbol parameter min max units v pp programming supply voltage 11.5 12.5 v i pp programming supply current 10 ma i cc v cc supply current 30 ma 1/t clcl oscillator frequency 3 33 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 s t ghsl v pp hold after prog 10 s t glgh prog width 0.2 1 s t avqv address to data valid 48t clcl t elqv enable low to data valid 48t clcl t ehqz data float after enable 048t clcl t ghbl prog high to busy low 1.0 s t wc byte write cycle time 50 s t glgh t ghsl t avgl t shgl t dvgl t ghax t avqv t ghdx t ehsh t elqv t wc busy ready t ghbl t ehqz p1.0 - p1.7 p2.0 - p2.5 p3.4 ale/prog port 0 logic 1 logic 0 ea/v pp v pp p2.7 (enable) p3.0 (rdy/bsy) programming address verification address data i n data o u t
at89s52 20 figure 16. flash memory serial downloading flash programming and verification waveforms ? serial mode figure 17. serial programming waveforms p1.7/sck data output instruction input clock in 3-33 mhz p1.5/mosi v ih xtal2 rst xtal1 gnd v cc at89s52 p1.6/miso v cc 7654 32 10
at89s52 21 notes: 1. the signature bytes are not readable in lock bit modes 3 and 4. 2. b1 = 0, b2 = 0 ---> mode 1, no lock protection b1 = 0, b2 = 1 ---> mode 2, lock bit 1 activated b1 = 1, b2 = 0 ---> mode 3, lock bit 2 activated b1 = 1, b1 = 1 ---> mode 4, lock bit 3 activated after reset signal is high, sck should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. no pulsing of reset signal is necessary. sck should be no faster than 1/16 of the system clock at xtal1. for page read/write, the data always starts from byte 0 to 255. after the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. then the next instruction will be ready to be decoded. table 9. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte 4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx 0110 1001 (output) enable serial programming while rst is high chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash memory array read program memory (byte mode) 0010 0000 xxx read data from program memory in the byte mode write program memory (byte mode) 0100 0000 xxx write data to program memory in the byte mode write lock bits (2) 1010 1100 1110 00 xxxx xxxx xxxx xxxx write lock bits. see note (2). read lock bits 0010 0100 xxxx xxxx xxxx xxxx xx xx read back current status of the lock bits (a programmed lock bit reads back as a ?1?) read signature bytes (1) 0010 1000 xxx xxx xxxx signature byte read signature byte read program memory (page mode) 0011 0000 xxx byte 0 byte 1... byte 255 read data from program memory in the page mode (256 bytes) write program memory (page mode) 0101 0000 xxx byte 0 byte 1... byte 255 write data to program memory in the page mode (256 bytes) d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 a12 a11 a10 a9 a8 b2 b1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 lb3 lb2 lb1 a5 a4 a3 a2 a1 a0 a12 a11 a10 a9 a8 a12 a11 a10 a9 a8 } each of the lock bits needs to be activated sequentially before mode 4 can be executed.
at89s52 22 serial programming characteristics figure 18. serial programming timing mosi miso sck t ovsh t shsl t slsh t shox t sliv table 10. serial programming characteristics, t a = -40 c to 85 c, v cc = 4.0 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency 0 33 mhz t clcl oscillator period 30 ns t shsl sck pulse width high 2 t clcl ns t slsh sck pulse width low 2 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 10 16 32 ns t erase chip erase instruction cycle time 500 ms t swc serial byte write cycle time 64 t clcl + 400 s
at89s52 23 notes: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum v cc for power-down is 2v. absolute maximum ratings* operating temperature.................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage ............................................ 6.6v dc output current...................................................... 15.0 ma dc characteristics the values shown in this table are valid for t a = -40c to 85c and v cc = 4.0v to 5.5v, unless otherwise noted. symbol parameter condition min max units v il input low voltage (except ea )-0.50.2 v cc -0.1 v v il1 input low voltage (ea )-0.50.2 v cc -0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage (xtal1, rst) 0.7 v cc v cc +0.5 v v ol output low voltage (1) (ports 1,2,3) i ol = 1.6 ma 0.45 v v ol1 output low voltage (1) (port 0, ale, psen ) i ol = 3.2 ma 0.45 v v oh output high voltage (ports 1,2,3, ale, psen ) i oh = -60 a, v cc = 5v 10% 2.4 v i oh = -25 a 0.75 v cc v i oh = -10 a 0.9 v cc v v oh1 output high voltage (port 0 in external bus mode) i oh = -800 a, v cc = 5v 10% 2.4 v i oh = -300 a 0.75 v cc v i oh = -80 a 0.9 v cc v i il logical 0 input current (ports 1,2,3) v in = 0.45v -50 a i tl logical 1 to 0 transition current (ports 1,2,3) v in = 2v, v cc = 5v 10% -650 a i li input leakage current (port 0, ea ) 0.45 < v in < v cc 10 a rrst reset pulldown resistor 10 30 k ? c io pin capacitance test freq. = 1 mhz, t a = 25c 10 pf i cc power supply current active mode, 12 mhz 25 ma idle mode, 12 mhz 6.5 ma power-down mode (1) v cc = 5.5v 50 a
at89s52 24 ac characteristics under operating conditions, load capacitance for port 0, ale/prog , and psen = 100 pf; load capacitance for all other outputs = 80 pf. external program and data memory characteristics symbol parameter 12 mhz oscillator variable oscillator units min max min max 1/t clcl oscillator frequency 0 33 mhz t lhll ale pulse width 127 2t clcl -40 ns t avll address valid to ale low 43 t clcl -25 ns t llax address hold after ale low 48 t clcl -25 ns t lliv ale low to valid instruction in 233 4t clcl -65 ns t llpl ale low to psen low 43 t clcl -25 ns t plph psen pulse width 205 3t clcl -45 ns t pliv psen low to valid instruction in 145 3t clcl -60 ns t pxix input instruction hold after psen 00ns t pxiz input instruction float after psen 59 t clcl -25 ns t pxav psen to address valid 75 t clcl -8 ns t aviv address to valid instruction in 312 5t clcl -80 ns t plaz psen low to address float 10 10 ns t rlrh rd pulse width 400 6t clcl -100 ns t wlwh wr pulse width 400 6t clcl -100 ns t rldv rd low to valid data in 252 5t clcl -90 ns t rhdx data hold after rd 00ns t rhdz data float after rd 97 2t clcl -28 ns t lldv ale low to valid data in 517 8t clcl -150 ns t avdv address to valid data in 585 9t clcl -165 ns t llwl ale low to rd or wr low 200 300 3t clcl -50 3t clcl +50 ns t avwl address to rd or wr low 203 4t clcl -75 ns t qvwx data valid to wr transition 23 t clcl -30 ns t qvwh data valid to wr high 433 7t clcl -130 ns t whqx data hold after wr 33 t clcl -25 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t clcl -25 t clcl +25 ns
at89s52 25 external program memory read cycle external data memory read cycle t lhll t lliv t pliv t llax t pxiz t plph t plaz t pxav t avll t llpl t aviv t pxix ale psen port 0 port 2 a8 - a15 a0 - a7 a0 - a7 a8 - a15 instr in t lhll t lldv t llwl t llax t whlh t avll t rlrh t avdv t avwl t rlaz t rhdx t rldv t rhdz a0 - a7 from ri or dpl ale psen rd port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data in instr in
at89s52 26 external data memory write cycle external clock drive waveforms t lhll t llwl t llax t whlh t avll t wlwh t avwl t qvwx t qvwh t whqx a0 - a7 from ri or dpl ale psen wr port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data out instr in t chcx t chcx t clcx t clcl t chcl t clch v - 0.5v cc 0.45v 0.2 v - 0.1v cc 0.7 v cc external clock drive symbol parameter min max units 1/t clcl oscillator frequency 0 33 mhz t clcl clock period 30 ns t chcx high time 12 ns t clcx low time 12 ns t clch rise time 5 ns t chcl fall time 5 ns
at89s52 27 shift register mode timing waveforms ac testing input/output waveforms (1) note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing mea- surements are made at v ih min. for a logic 1 and v il max. for a logic 0. float waveforms (1) note: 1. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs. serial port timing: shift register mode test conditions the values in this table are valid for v cc = 4.0v to 5.5v and load capacitance = 80 pf. symbol parameter 12 mhz osc variable oscillator units min max min max t xlxl serial port clock cycle time 1.0 12t clcl s t qvxh output data setup to clock rising edge 700 10t clcl -133 ns t xhqx output data hold after clock rising edge 50 2t clcl -80 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10t clcl -133 ns t xhdv t qvxh t xlxl t xhdx t xhqx ale input data clear ri output data write to sbuf instruction clock 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 set ti set ri 8 valid valid valid valid valid valid valid valid 0.45v test points v - 0.5v cc 0.2 v + 0.9v cc 0.2 v - 0.1v cc v load + 0.1v timing reference points v load - 0.1v load v v ol + 0.1v v ol - 0.1v
at89s52 28 ordering information speed (mhz) power supply ordering code package operation range 24 4.0v to 5.5v at89s52-24ac at89s52-24jc at89s52-24pc 44a 44j 40p6 commercial (0 c to 70 c) at89s52-24ai at89s52-24ji at89s52-24pi 44a 44j 40p6 industrial (-40 c to 85 c) 33 4.5v to 5.5v at89s52-33ac AT89S52-33JC at89s52-33pc 44a 44j 40p6 commercial (0 c to 70 c) = preliminary availability package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-pin, 0.600" wide, plastic dual inline package (pdip)
at89s52 29 packaging information *controlling dimension: millimeters 1.20(0.047) max 10.10(0.394) 9.90(0.386) sq 12.21(0.478) 11.75(0.458) sq 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) 0.20(.008) 0.09(.003) 0 7 0.80(0.031) bsc pin 1 id 0.45(0.018) 0.30(0.012) .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq 2.07(52.6) 2.04(51.8) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.900(48.26) ref 44a, 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 44j, 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) 40p6, 40-pin, 0.600" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-011 ac
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